1. Related Application
This invention is related to U.S. patent application entitled, "Boolean and Data Movement Accelerator," filed concurrently herewith.
2. Field of the Invention
This invention is related generally to computer systems and more particularly to I/O subsystem architectures.
3. Description of Related Art
To extend overall computer system performance, designers have sought to improve input/output (I/O) performance to keep pace with the ever increasing processing speed of modern and future host processors. The development of computers with intelligent I/O subsystems is one such improvement that is believed to help eliminate the I/O bottleneck. Such a computer is divided into a local bus, a primary bus, and a secondary bus, where the I/O devices normally reside on the secondary bus, the host system resides on the primary bus, and a subsystem processor is coupled to the local bus. The primary and secondary buses are coupled by a bridge. Redirecting interrupt-intensive I/O tasks to the subsystem processor and away from the host processor frees host resources such as host memory and the primary bus. This allows the development of I/O capability independently of the host system. The I/O subsystem may be one which complies with the industry-standard Intelligent I/O (I.sub.2 O.RTM.) interface for Peripheral Components Interconnect (PCI) bus applications.
The I/O subsystem typically includes a single integrated circuit die known as an I/O processor (IOP). The salient functions traditionally integrated on the single chip I/O processor include part of the local bus, a core (subsystem) processor, a memory controller, the bridge, and address translation units that are coupled between the local bus and the primary and secondary buses. Some applications of the I/O processor are described below as two currently popular system applications: storage and networking.